1. Field of the Invention
The present invention relates to a test structure for inspecting an electrical device; and more particularly, relates to a test structure, fabricated by double patterning technology, for inspecting an electrical device.
2. Description of the Prior Art
In material processing methodologies, pattern etching comprises application of a thin layer of light-sensitive material, such as photo-resist, to an upper surface of a substrate that is subsequently patterned to fabricate a mask suitable for transferring this pattern to an underlying thin film on a substrate. The patterning of the light-sensitive material generally involves exposure by a radiation source through a reticle (and associated optics) of the light-sensitive material using, for example, a photo-lithography system, followed by the removal of the irradiated regions of the light-sensitive material (as in a case of positive photoresist), or non-irradiated regions (as in a case of negative resist) using a developing solvent. Moreover, this mask layer may comprise multiple sub-layers.
In a pattern of dense lines and spaces printed at a fine resolution, a line width critical dimension (CD) of the lines is substantially equal to the space width of the spaces, so that the line width is half of the pitch at which the lines are disposed in the pattern. A maximum density at which lines can be printed is determined by the characteristics of a lithographic apparatus as well as the printing process. The apparatus characteristics include characteristics of the imaging system (e.g. an optical projection system) of the apparatus. The process characteristics include characteristics of exposure and development processes, and that of the resist material.
More recently, a double patterning approach has been introduced to allow patterning of smaller features at a smaller pitch than what is currently possible with standard lithographic techniques. One approach to reduce the feature size is to use standard lithographic pattern and etch techniques on the same substrate twice, thereby forming larger number of patterns spaced closely together to achieve a smaller feature size than would be possible by single exposure. In, for example, a dual-trench double patterning process for printing dense lines and spaces, a first and a second pattern of spaces are etched, in interleaved position, in a target layer. The target layer may be, for example, a sacrificial etch mask to be used for an etching of a layer underlying the target layer. Such a double patterning technique exploits the possibility to print, in a single exposure process and for a given numerical aperture (NA) and wavelength λ, a semi-dense pattern of spaces at a width CDdp below the value CD when the spaces are arranged at a pitch greater than 2k1 (λ/NA). Thus, such a pattern is not a dense pattern in the sense that the widths of the lines and spaces are equal. Instead, a width of the lines is, for example, a factor three times the width CDdp of the spaces. For printing such a semi dense pattern of line-shaped spaces or a semi dense pattern of trenches, wherein CDdp<CD, generally a positive tone resist is used.
A dual-trench double patterning process for printing dense lines is characterized by the following three steps. In a first step, a first semi dense pattern of spaces is printed in resist material. After development of the resist material, the remaining resist material mask is used as etch mask for the second step. In the second step, the spaces are transferred to a target layer by applying an anisotropic etching process to the substrate, and the resist material mask is then stripped. In some cases, a Reactive Ion Etching (RIE) process is used. In a third step, the target layer is again coated with resist material, and a second semi dense pattern of spaces is printed in the resist material. The second printing is arranged such that the spaces of the second pattern are positioned interleaved with respect to spaces etched in the target layer. As a result of the interleaving, a subsequent etching of the target layer, again using an RIE process, yields lines of target layer material protruding from the surface of the substrate. By interleaving two patterns of semi dense spaces, each pattern characterized by a space width CDdp and a pitch 4 CDdp, the resulting lines have a width equal to the space width CDdp, so that a dense line pattern is obtained.
A charged particle beam imaging system, such as an electron beam imaging (EBI) system, is increasingly applied in advanced IC chip manufacturing to detect fetal defects which would result in waste devices. EBI can be used to inspect defects such as an open defect, a short defect or a leakage defect on or underneath the wafer surface by detecting voltage contrast (VC) due to the surface charge induced gray level (GL) variation. For such purpose, semiconductor test structures of various shapes, building materials and electrical characteristics have been developed to more easily identify the location of the defects. Nowadays, as the size of the semiconductor device is rapidly shrinking, test structures with finer features are needed to correctly reproduce the device at interest. Therefore, it is desirable to fabricate scaled test structures with desired pattern layout and electrical characteristics utilizing the double patterning technique, so the testing of an interested device can be realistically carried out.